# 华为提出"τ缩放定律"，以侧向创新突破芯片与存储瓶颈

- 来源：Rohan Paul (@rohanpaul_ai)
- 发布时间：2026-05-25 15:08
- AIHOT 分数：67
- AIHOT 链接：https://aihot.virxact.com/items/cmpkvwus60an2sl017yjg4r7q
- 原文链接：https://x.com/rohanpaul_ai/status/2058807460572606946

## AI 摘要

华为提出τ缩放定律，旨在不依赖更先进制程的情况下，通过LogicFolding技术折叠逻辑模块、缩短信号传输距离来提升芯片性能与密度。华为称已量产采用此思路的381颗芯片，并计划于2031年实现等效1.4nm（14Å）密度，该定律以海思负责人何庭波命名。同样，华为在存储领域也展示了类似的“侧向创新”路径，其通过改变封装方式（Die-on-Board）而非追求最先进的NAND层数，推出了容量达122.88TB的AI SSD。

## 正文

🇨🇳 Huawei reveals a new chip design breakthrough under US sanctions pressure.

A design approach meant to close the gap with TSMC and Intel without relying only on smaller transistors， by making chip signals travel less distance.

They want 1.4nm-class density without owning the world's best lithography tools i.e. they are trying to replace Moore's Law with Tau Scaling Law.

To note， Huawei has been blocked from normal access to TSMC since the US tightened foreign direct product rules around Huawei in 2020， and TSMC later said it had not supplied Huawei since mid-September 2020.

Proposed τ Scaling as a new way to make chips faster when shrinking transistors is no longer delivering the same gains.

Said its next Kirin phone chip will be the first full test of Tau Scaling Law，

Old chip progress mostly came from making every transistor smaller， but Huawei's idea shifts the target from smaller geometry to shorter signal delay， meaning less time wasted while electrical signals crawl through wires， gates， memory paths， and system links.

LogicFolding attacks the circuit layout itself by folding logic blocks closer together， shortening critical wires， reducing resistance and parasitic capacitance， and letting signals switch faster with denser placement.

So LogicFolding is the circuit-level piece： it tries to place related logic closer together， shorten key wires， cut electrical drag from resistance and parasitic capacitance， and raise performance without needing a full manufacturing-node leap.

Huawei is also pushing the same timing idea across the full stack： transistors， circuits， chip architecture， software scheduling， and system interconnects all get tuned to reduce τ， the delay constant that limits speed and efficiency.

The bold claim is that Huawei has already mass-produced 381 chips using this thinking， and future high-end chips could reach density comparable to 14Å， or 1.4nm， without relying only on classic process shrinkage.

Says this path could reach 1.4nm-class， or 14Å-class， density by 2031， while TSMC and Intel target similar physical nodes around 2029.

Huawei calls it Her's Law， after He Tingbo， the chip leader who helped turn HiSilicon into Huawei's survival engine after US export controls.
---

huawei. com/en/news/2026/5/ieee-iscas-tau-scaling

### 引用推文

> Rohan Paul：🇨🇳 🇺🇸 China's Huawei's new 122TB SSD shows how export controls can move innovation sideways instead of simply stopping it. Huawei just built a 122.88TB AI S...