Rohan Paul@rohanpaul_ai

2026-05-27 22:45·36天前

AI 摘要

华为推出“LogicFolding”芯片设计技术，旨在不依赖单纯缩小晶体管制程，以缩小与竞争对手的差距。其核心思想是通过垂直堆叠活跃电路层，将关键信号路径“折叠”向上，从而缩短导线长度、减少寄生延迟并收紧时钟偏差，最终在不改变器件节点的情况下提升芯片频率。此技术并非传统3D封装，其深层创新在于将芯片拓扑结构本身变为一种性能缩放工具。华为指出，该技术能大幅压缩相邻触发器间的传播时间，收紧关键路径。预计其高端芯片将在2031年实现等效于14 Å（1.4 nm）工艺的晶体管密度。

Huawei's new breakthrough "LogicFolding".

To close the gap with TSMC and Intel without relying only on smaller transistors， by making chip signals travel less distance.

Their main ideas is that chip progress should now be measured by time saved， not just space shrunk.

What they call "τ scaling" - changes the question from "how small is the transistor？" to "where is time being lost？"

LogicFolding is Huawei's physical answer to that question inside a chip.

LogicFolding partitions digital， analog， and memory circuits across vertically stacked active tiers， so the chip behaves less like a city spread across a plain and more like a compact building with elevators between floors.

Because chip delay is often not just the transistor switching time， but the resistance and capacitance of wires between logic gates.

By folding critical paths upward into another active layer， the design can shorten wires， reduce parasitic delay， tighten clock skew， and raise frequency without changing the device node.

So LogicFolding is not simply "3D chips" as a packaging.

Its deeper idea is that topology has become a scaling tool.

When lithography stops giving easy gains， the next improvement may come from rearranging where logic， memory， power， and communication physically live.

HuaweiWhat is LogicFolding? For circuit design, it aggressively compresses propagation time between adjacent flip-flops, tightens critical path & enables chips to run...

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Rohan Paul@rohanpaul_ai · X

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