# 华为提出τ定律应对芯片制程瓶颈

- 来源：X.PIN (@thexpin)
- 发布时间：2026-05-29 22:45
- AIHOT 分数：65
- AIHOT 链接：https://aihot.virxact.com/items/cmpr2626s0a8qslno26zz8tnt
- 原文链接：https://x.com/thexpin/status/2060372079749562442

## AI 摘要

由于美国出口管制，华为在芯片先进制程竞赛中面临困难。为此，华为于2026年5月提出“τ（Tau）定律”，旨在为后摩尔时代的芯片性能提升提供新框架。该定律的核心是优化有效RC时间常数（τ）以提升信号传播速度。其方法是不完全依赖制程微缩，而是从晶体管、电路、芯片互连及系统架构四个层次进行优化，以压缩τ值。华为将其描述为中国公司首次提出具有全球影响力的后摩尔扩展框架。

## 正文

http://x.com/i/article/2060305879338029061

# Huawei can't win the Nanometer race. So it is changing the game.

Unable to compete at the frontier of transistor scaling， Huawei is betting that the future of chip performance lies in integration， interconnects， and light.

Huawei cannot reliably win the nanometer race. So it has decided to run a different one.

On May 25， 2026， He Tingbo， Huawei's borad member and president of semiconductor business， took the stage at the International Symposium on Circuits and Systems in Shanghai and announced what she called the τ （Tau） Law， a new principle for how chips should be made faster in an era when making transistors smaller is no longer a reliable path forward. Huawei described it as the first attempt by a Chinese company to articulate a post-Moore scaling framework with global ambitions. The announcement generated a wave of coverage， most of it focused on whether this constituted a genuine scientific contribution or a rebranding of known techniques.

Both framings miss the more consequential question： why is Huawei doing this at all， and what does it reveal about where the company is placing its bets？

The answer starts with a set of circumstances Huawei did not choose， and a moment in the industry's trajectory that made those circumstances easier to work with.

The timing is not accidental. As transistor scaling slows globally， AI systems are becoming increasingly constrained by data movement rather than raw compute. The bottleneck is shifting from how fast a single chip can calculate to how efficiently thousands of chips can share data across a system. The industry was already moving toward advanced packaging， chiplets， and optical interconnects to address that shift. Huawei's contribution was to turn those scattered trends into a single narrative， and claim the naming rights before anyone else did.

Since 2020， U.S.-led export controls have effectively cut Huawei off from the ecosystem required to manufacture chips at the industry's leading edge. The result is that Huawei cannot access leading-edge manufacturing on the same terms as Apple， Nvidia， or Qualcomm. The Mate 60's appearance of 7nm-class chips， achieved through SMIC， showed that the door is not entirely shut. But competing at the industry's true frontier has become extraordinarily difficult in a way that is structural， not temporary.

That frontier has a straightforward competitive logic. Smaller transistors fit more computing power into the same area， consume less energy per operation， and run faster. This is what Moore's Law predicted in 1965 and what the industry has organized itself around ever since. Every two years or so， the leading foundries push to a new node： 7nm， 5nm， 3nm. The companies that can access those nodes gain a measurable performance advantage over those that cannot.

Competing there， at the very frontier， is what Huawei cannot currently do on equal terms. That is the constraint within which the τ Law was designed.

## A Different Variable to Optimize

The τ Law proposes an answer to that constraint. In Huawei's formulation， τ refers to the effective RC time constant that governs how quickly signals can propagate and switch states within a chip. Smaller τ means faster signals， more operations per second， higher effective performance.

Moore's Law， underneath all the transistor-count language， was always producing performance gains by reducing τ： shrink the transistors， shorten the wires connecting them， signals arrive faster. Huawei's argument is not that this was wrong. It is that there are other ways to reduce τ that do not require a new process node： through the circuit layout， the chip architecture， and the systems connecting chips together.

Huawei defines a four-layer optimization stack： the transistor itself， the circuit connecting transistors， the chip connecting circuits， and the system connecting chips. Each layer has its own version of τ， and each offers opportunities to compress signal travel time without shrinking transistor dimensions. The τ Law is a framework for pursuing all four simultaneously.

Here is the honest assessment of what this represents： Huawei did not discover this direction. The physics pointing toward it， with RC delay as the binding constraint as geometric scaling slows， has been in semiconductor textbooks for decades. Intel， TSMC， and Samsung are all working on versions of the same techniques. What Huawei did was name the direction， formalize it into a single framework， and build a public roadmap around it. That is a different kind of contribution than inventing the underlying physics. But it is not nothing. Moore's Law itself was not a discovery of new physics. It was a prediction that became a commitment that became a coordination mechanism for an entire industry.

## Folding Is Not Stacking

The most tangible expression of the τ Law at the chip level is Logic Folding， and understanding it requires separating it from something it superficially resembles： conventional 3D chip stacking.

The semiconductor industry has been stacking chips for years. TSMC's SoIC， Intel's Foveros， and Samsung's X-Cube all take multiple finished chips and connect them vertically to reduce the distance signals travel between them. It is a genuine and increasingly important technique. But each chip in the stack is still internally structured the same way it always was： circuits laid flat across a single layer， signals running long horizontal paths to reach neighboring gates.

Logic Folding addresses the interior of the chip， not the space between chips. Rather than finishing the chip and then connecting it to others， Huawei redesigns the circuit layout during the design phase， redistributing logic gates across multiple vertical layers within a single chip. Connections between layers are made through face-to-face hybrid bonding， routing signals vertically across short distances rather than horizontally across long ones.

3D stacking shortens the distance between chips. Logic Folding shortens the distance inside a chip. One is a packaging innovation applied after manufacture. The other is a design innovation applied before it. They address different layers of the same problem， which is also why they are complementary rather than competing.

On the first commercial implementation， the new Kirin chip expected this autumn， Huawei claims transistor density rises from 155 million to 238 million per square millimeter， and says energy efficiency improves by 41%.

These numbers come from Huawei and have not been independently verified. What can be said without qualification is that the improvement is achieved without a new manufacturing process， on existing foundry infrastructure， which is the point the τ Law is making. The goal is approaching the transistor density associated with leading-edge nodes through design rather than fabrication.

This is a meaningful achievement if the numbers hold up. It is also， importantly， a packaging and integration achievement more than a transistor achievement. The performance gain comes from rethinking how circuit elements connect to each other， not from making them individually smaller. And that logic， followed to its conclusion at the system level， leads directly to co-packaged optics.

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