# 晶圆级芯片I/O带宽瓶颈分析

- 来源：SemiAnalysis (@SemiAnalysis_)
- 发布时间：2026-08-28 08:00
- AIHOT 分数：37
- AIHOT 链接：https://aihot.virxact.com/items/cmtc7dz3201ecrozkk1gsyeks
- 原文链接：https://x.com/SemiAnalysis_/status/2093126655040507930

## AI 摘要

片外带宽一直是晶圆级芯片的短板。WSE-3 拥有惊人的晶圆上 SRAM 带宽，但一旦数据需要离开晶圆，一切都会变慢。这之所以重要，是因为晶圆仅能容纳 44GB 的 SRAM，因此大模型会被分散到多块晶圆上，而每增加一块晶圆，就意味着有更多数据需要穿越这条带宽受限的 I/O 路径。长上下文会让情况更糟，因为 KV 缓存会进一步推高所需晶圆数量。(1/3)🧵 图片来源：Cerebras

## 正文

Off-chip bandwidth has always been the weak point of wafer-scale. The WSE-3 has staggering on-wafer SRAM bandwidth, but everything slows down the moment data has to leave the wafer. That mattered because the wafer only holds 44GB of SRAM, so big models get spread across many wafers, and every extra wafer means more traffic crossing that starved I/O path. Long context makes it worse, since KV cache balloons the wafer count further. (1/3)🧵
Image Source: Cerebras