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High-bandwidth memory (HBM) has grown from 52% to 63% of total AI chip component spending between Q1 2024 and Q4 2025. These estimates are an average across all AI chips designed by Nvidia, AMD, Google, and Amazon, weighted by production volume. As a share of spend, logic dies stayed roughly flat near 13%, while advanced packaging fell from 19% to 15% and auxiliary components fell from 15% to 9%. In absolute terms, HBM spend across these four designers grew from roughly $12 billion in 2024 to $32 billion in 2025, a faster year-over-year increase than any other component.
HBM will likely account for an even larger share in 2026 as memory supply remains tight and prices rise. Hyperscalers are already anticipating this in capex guidance: Microsoft’s $190 billion FY2026 capex outlook includes about $25 billion from higher component prices, while Meta raised its 2026 capex range by $10 billion, citing higher component prices.
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For each AI chip designed by Nvidia, AMD, Google, and Amazon, we estimate the per-chip cost of four component categories: memory (HBM), logic dies, advanced packaging (CoWoS), and auxiliary components. We then multiply those per-chip costs by estimated quarterly production volumes to get total component spending in each category, and compute each category’s share of total component spending per quarter from Q1 2024 to Q4 2025.
We find that memory’s share rose from 52% to 63% over this period, while packaging fell from 19% to 15% and auxiliary components from 15% to 9%. Logic die share stayed roughly constant near 13–14%. Total component spend on AI chips grew from approximately $22 billion in 2024 to $52 billion in 2025, with HBM spending alone accounting for roughly $20 billion of that increase.
Data
Component cost estimates are drawn from our AI Chip Components explorer, which builds chip-level bills of materials from financial disclosures, supplier filings, and analyst reports. Four component categories are tracked:
Memory: HBM stacks (HBM3, HBM3e).
Logic: advanced-node logic dies (3 - 5nm).
Packaging: TSMC CoWoS advanced packaging.
Auxiliary: substrate, power delivery, and other non-logic, non-memory inputs.
See the explorer’s methodology documentation to learn more.
Analysis
Each unit of a component has some cost uncertainty, including the price of an HBM stack, a logic die, or a CoWoS package. We model each chip’s per-component cost with a 90% confidence interval and the share is a ratio of this component’s cost over the total, so both numerator and denominator are uncertain. We show two bounds on the share: