引言
今天，Qwen 团队开源了 Qwen3.8-Flash-Next，这是一个多模态 MoE 模型，也是 Qwen4 架构的早期预览版。它对 Qwen4 所扮演的角色，与 Qwen3-Next 对 Qwen3.5 所扮演的角色相同。Gated DeltaNet + Gated Attention 的混合设计已从 Qwen3.5 一直沿用到 Qwen3.8。在与 Qwen、NVIDIA 和 AMD 团队的合作下，SGLang 为该模型提供了首发日（day-0）支持。
Qwen3.8-Flash-Next 在多个方面升级了架构：
- GDN + QSA 混合注意力：Gated DeltaNet（GDN）高效压缩历史信息，而 Qwen 稀疏注意力（QSA）则使用轻量级索引器在微块粒度上选择重要上下文，从而保持长序列注意力成本的低廉。
- Gated Residual（GR）：将残差流拓宽为 4 个分支，并通过动态门控控制读写，强化跨层信息流动。
- N-gram 嵌入：基于局部上下文进行查找，为常见短语和局部模式提供额外表示，以极少的额外计算扩展模型容量。
- 混合架构：一个 125B 参数的主模型，辅以额外的 51B N-gram 嵌入，每个 token 激活 6B 参数。共 48 层：36 层 GDN 线性注意力层和 12 层 QSA 稀疏注意力层。MoE 层使用 512 个专家，采用 top-10 路由。
- 我们量化出的一个 NVFP4 检查点：RadixArk/Qwen3.8-Flash-Next-NVFP4，在首发日（day-0）发布。
- N-Gram 嵌入：将 N-gram 嵌入卸载到主机内存可大幅降低 GPU 内存占用，异步预取使其与模型计算重叠，几乎不增加额外成本。
- Gated Residual，与 NVIDIA 合作构建并通过 FlashInfer 发布：通过低延迟单 GEMM 路径实现高性能 Mix/Combine HyperConnection 算子（内核级 2.05 倍加速）。
- GDN+QSA：针对 GDN+QSA 混合架构的 KV cache 内存管理，兼容 Radix Cache。
- 投机解码：为 MTP 草稿模型提供索引复用功能，在长上下文长度下削减草稿模型的索引器耗时。在 B200 上以 TP4 运行时，NVFP4 检查点在 batch size 为 1 且启用 MTP 的情况下，解码速度为 540 tok/s，接受长度为 3.3（包含奖励 token）。
启动命令和按工作负载的配置指南位于 SGLang Cookbook 中。
模型架构
- GDN+QSA 混合架构：遵循 Qwen3.5 中引入的架构设计，Qwen3.8-Flash-Next 采用了 GDN + Attention 混合架构：每 4 层中，有 3 层 GDN 层将历史信息压缩为固定大小的状态，而剩余 1 层则对完整上下文执行精确检索。对于全局 Attention 层，Qwen3.8-Flash-Next 进一步引入了 Qwen 稀疏注意力（QSA），以解决随着上下文变长，计算量和 KV 缓存内存访问成本都大幅增长的问题。稀疏注意力通过仅关注重要上下文来减少长序列计算量。QSA 更进一步：它将序列聚合为微块，在块级别估计重要性，然后选择最相关的区域，从而同时降低索引开销和注意力成本。
- 门控残差（GR）：结合了两个思路：遵循 Hyper-Connection，它将残差流拓宽为多个分支；同时将 GatedNorm 风格的逐元素动态门控引入残差读取中。原本单一的残差流被扩展为 4 个并行分支，使模型能够根据当前内容动态决定从每个分支读取多少信息以及写回多少信息。
- N-gram 嵌入：使用“当前 token 加上前几个 token”构成的局部上下文进行查找，为常见短语和局部模式提供额外的表示，同时几乎不增加每个 token 的计算开销。N-gram 嵌入可以完全驻留在主机内存中以节省 GPU 内存：查找位置预先计算并异步预取，因此它不会永久占用 GPU 内存。最终，模型仅在网络起始位置附近使用一个 N-gram 嵌入层，以相对较低的成本增加了一个大规模的“局部模式记忆”。
- IndexShare MTP：由草稿扩展阶段在目标模型刚接受的 token 上计算出的 QSA top-k 选择结果，会在整个 MTP 迭代期间被保留，因此每一步草稿解码都会跳过索引器，直接读取那份冻结的选择结果以及此后草稿生成的位置。在长上下文场景下，这能显著加速 MTP 草稿生成步骤。
Qwen 稀疏注意力：粗粒度检索，精粒度关注
Qwen3.8-Flash-Next 使用压缩比为 4（即 c4）的压缩版 QSA。每个 QSA 层有两条路径：一个轻量级索引器决定关注哪里，而稀疏 GQA 则从原始注意力 K/V 缓存中读取被选中的条目。
索引器投影出四个 128 维的查询头和一个共享的键头。每四个原始索引键在 FP32 精度下取平均、归一化，并与第一个 token 的 MRoPE 位置一起旋转，从而形成一个压缩键。一个查询对可见的压缩块进行打分，使用
QSA 保留最佳的 512 个块，将它们展开回 2048 个逻辑 token 位置，并追加当前未完成块中的零到三个 token。因此，最终的稀疏注意力最多能看到 2051 个位置。重要的是，压缩键仅仅是一个索引：最终的 softmax 和值聚合使用的是原始的、未压缩的 K/V。
这意味着 QSA 用少量的缓存容量换取大幅降低的长上下文计算量和内存流量。索引器扫描大约少量键，然后稀疏注意力读取约 2K 个完整 K/V 条目，而不是全部。模型层面的 KV 节省来自混合布局：48 层中只有 12 层存储不断增长的注意力 K/V，而其余 36 个 GDN 层使用固定大小的状态，并非通过在 QSA 层内部丢弃 K/V 来实现。
SGLang 仅将索引器附加到全注意力层，并复用它们的 MRoPE 实现。原始 K/V 保留在常规的分页池中。QSA 每四个 token 增加一个 BF16 压缩索引键；未完成块的原始键存放在每个请求四个槽位的环形缓冲区中。这避免了为整个上下文保留原始索引键，并将 QSA 的索引缓存开销降低了 80%。按页对齐的 full_slot / 4 寻址方式让压缩缓存能够遵循 Radix Cache 的所有权，而无需单独的生命周期管理。
在预填充阶段，一个定制的 GPU 内核计算索引分数，一个快速的 top-k 操作选择块，然后 Triton 展开索引并运行稀疏 GQA。解码阶段使用同一评分器的分页版本，压缩所选的原生 K/V，并在 Blackwell 上分派给 TRTLLM-Gen，否则使用打包的 FlashAttention。索引器可以在第二个 CUDA 流上与主 Q/K/V 投影重叠执行，元数据路径与 CUDA 图兼容。
IndexShare MTP：在草稿步骤间复用 QSA 选择
QSA 层运行一个索引器，挑选要关注的 token，然后仅对这些 token 执行稀疏注意力。第二阶段有固定的 token 预算；第一阶段将其查询与所有 ⌈L/4⌉ 个压缩块进行评分，因此一旦超过几千个 token，决定该层成本的就是索引器，而非其馈送的注意力。推测解码将其放大：使用 --speculative-num-steps N 时，一次 MTP 迭代需要 N 次索引器调用（N - 1 次草稿解码前向传播加上一次草稿扩展）才能将草稿推进最多 N 个位置。
因此，草稿解码步骤完全不再运行索引器。每次 MTP 迭代都以对目标刚接受的 token 进行草稿扩展开始，而该过程无论如何都会运行索引器；每个请求最后被接受的行在此处被捕获，并由整个草稿循环复用，查找时额外填充 N + 1 列，填入自捕获以来草稿出的位置，这样草稿仍能看到自己进行中的 token。该选择是一个逻辑 token 索引列表，而请求只会不断增长，因此永远不会越界；并且由于查询在 L 中最多移动了 N 个位置，复用的排序本质上与索引器本会重新计算的排序一致；接受长度不变。每次 MTP 迭代中草稿的索引器工作从 N 次调用降为一次。那些仅为喂给索引器而存在的小型元数据内核，包括压缩解码视图以及待处理环和组环布局，也一并从草稿解码步骤中移除。
HyperConnection 内核优化
HyperConnection（HC）维护四条并行残差流，而 Attention 和 MoE 则在单一隐藏状态上运行。因此，每个模块都使用 Mix 从四条流中读取数据，并用 Combine 将其输出写回。此处，M 为单次调用处理的 token 数量：在解码和推测验证阶段它很小，但在预填充阶段可达数千。我们根据 M 的大小分派到不同的内核。
Mix
Mix 使用低秩投影生成逐元素门控，并将四条残差流缩减为一个隐藏状态。当 M ≤ 16 时，我们使用 FlashInfer PR #4266 中的低延迟 split-K CuTe GEMM。Split-K 对 K 维度进行划分，使多个 CTA 能并行处理同一输出区域，从而弥补 M 维度并行度不足的问题。SiLU、Sigmoid、门控以及最终归约都被融合到两个 GEMM 尾声（epilogue）中，避免了对全局内存的中间写入。上投影权重在离线状态下重新排序，使得每个输出的四个门控值可以在 tile 内部进行局部归约。对于更大的 M，实现则使用 cuBLAS，因为它在这些形状下效率更高。
在 NVIDIA B300 上，当 M = 4 时，融合路径将 Mix 延迟从 12.36 微秒降至 6.03 微秒，内核级加速达 2.05 倍。在与之前 Triton 路径的端到端推测解码基准测试中，吞吐量提升了 7.6%。
Combine
Combine 计算四个注入系数，并对四条流执行残差更新。对于较大的 M，一个融合内核会在单次遍历中处理每个 token 行。在 M 较小时，这种映射暴露出的 CTA 数量过少，因此 M ≤ 32 的路径会沿隐藏维度拆分每一行。由此产生的双内核实现提供了足够的并行度，同时保持了参考 FP32 累加顺序和逐位一致的输出。
在 M = 4 时，拆分路径将 Combine 延迟从 4.17 微秒降至 2.13 微秒，内核级加速达 1.96 倍。在与原始每行一个 CTA 内核的独立端到端基准测试中，吞吐量提升了 5.49%。对于较大的 M，融合内核比基于 cuBLAS 的基线快达 2.54 倍，并达到 6144 GB/s 的有效带宽。
形状感知调度让 HC 能够针对低延迟解码和大规模预填充分别采用合适的执行路径。
逐层嵌入（PLE）
架构
该模型将 PLE（一种基于哈希寻址的学习式 N-gram 嵌入记忆）放置在第二个解码器块（配置层 ID 为 2，对应从零开始的索引 1）。其 512 亿个嵌入参数（BF16 格式下约 95.4 GiB）是固定的模型权重，而非 KV 缓存或可变的注意力记忆。
对于 token x_t，八个 2-gram 哈希头使用 (x_{t-1}, x_t)，八个 3-gram 哈希头使用 (x_{t-2}, x_{t-1}, x_t)，共生成 16 个嵌入行 ID。每行贡献 160 个值，这些值被拼接成形状为 [2560] 的 E_t。
位于第二个解码器块的 PLE。稀疏 N-gram 检索被门控到四个 HC 分支中，然后进入 HC Mix。SGLang 将词表并行表分片移至锁页主机内存，并且每个 token 仅收集选中的 16 行。
第四行通过将门控值与其短卷积输出相加来形成 PLE 增量；第五行将该增量注入 HC 状态。PLE 维护两个请求局部状态：用于哈希的两个最近 token ID，以及形状为 [10240, 9] 的短卷积历史。目标模型在预填充、解码和目标验证阶段均保留 PLE；仅单层 MTP 草稿模型将其禁用。
稀疏锁页主机内存卸载
由于每个 token 仅涉及 16 行，SGLang 将每个 rank 的词表并行表分片保留在锁页主机内存中，并使用 Triton UVA 内核将选中的行收集到一个小型 BF16 GPU 缓冲区中。一个专用的 CUDA 流将收集操作与第一个解码器块重叠执行。现有的 TP 归约和 DP 收集/分发路径保持不变：卸载仅改变存储位置，不改变表所有权或 PLE 计算。当有效模型 dtype 为 BF16 时，此 CUDA 路径默认启用，并且与 KV 缓存或通用层卸载保持独立。
在 H200 上，采用 TP4 和 MTP-213（2 个草稿步骤，top-k 为 1，每次目标验证 3 个草稿 token）时，卸载将目标模型权重从每 GPU 83.91 GiB 降至 60.45 GiB（减少 23.46 GiB），并在相同内存占比下将分配的 KV 容量从 1.84M 提升至 3.28M token（增加 78.54%）。在 1、2 和 4 个并发请求下，匹配吞吐量基本不变（几何平均值 -0.07%）。四个固定提示词各生成 128 个 token，输出 ID 完全一致；首个案例记录的所选 token logprob 轨迹也完全匹配。
致谢
本工作是 RadixArk 的 SGLang 团队、Qwen、NVIDIA 和 AMD 之间的合作成果。
SGLang 社区：Qiaolin Yu、Yuhao Yang、Cheng Wan、Xinyuan Tong、Zijie Xia、Ke Bao、Mingyi Lu、Haoguang Cai、Banghua Zhu、Ying Sheng
Qwen：Yi Zhang、Yizhong Cao、Guangda Liu
AMD：Andy Luo、Haichen Zhang
NVIDIA：NVIDIA 与 SGLang 联合优化了 Qwen3.8-Flash-Next 在 Blackwell 和 Hopper 上的性能。
Introduction
Today, the Qwen team open-sourced Qwen3.8-Flash-Next, a multimodal MoE model and an early preview of the Qwen4 architecture. It plays the same role for Qwen4 that Qwen3-Next played for Qwen3.5. The Gated DeltaNet + Gated Attention hybrid design has been used from Qwen3.5 through Qwen3.8. In collaboration with the Qwen, NVIDIA, and AMD teams, SGLang provides day-0 support for the model.
Qwen3.8-Flash-Next upgrades the architecture in several areas:
- GDN + QSA hybrid attention: Gated DeltaNet (GDN) efficiently compresses the history, while Qwen Sparse Attention (QSA) uses a lightweight indexer to select important context at micro-block granularity, keeping long-sequence attention costs low.
- Gated Residual (GR): widens the residual stream into 4 branches and controls reads and writes with a dynamic gate, strengthening cross-layer information flow.
- N-gram Embedding: performs lookups based on the local context, providing additional representations for common phrases and local patterns, expanding model capacity with very little extra computation.
- Hybrid architecture: a 125B-parameter main model, supplemented by an additional 51B N-gram Embedding, with 6B parameters activated per token. 48 layers in total: 36 GDN linear attention layers and 12 QSA sparse attention layers. MoE layers use 512 experts with top-10 routing.
- An NVFP4 checkpoint we quantized: RadixArk/Qwen3.8-Flash-Next-NVFP4, released day-0.
- N-Gram Embedding: offloading the N-gram embedding to host memory greatly reduces GPU memory usage, and asynchronous prefetching overlaps it with model computation at almost no extra cost.
- Gated Residual, built with NVIDIA and shipped through FlashInfer: high-performance Mix/Combine HyperConnection operators via a low-latency single-GEMM path (2.05× kernel-level speedup).
- GDN+QSA: KV cache memory management for the GDN+QSA hybrid architecture, compatible with Radix Cache.
- Speculative Decoding: an index-reuse feature for the MTP draft model, cutting the draft model's indexer time at long context lengths. At TP4 on B200, the NVFP4 checkpoint decodes at 540 tok/s for batch size 1 with MTP, at an accept length of 3.3 (which includes the bonus token).
Launch commands and per-workload configuration guidance live in the SGLang Cookbook.
Model Architecture
- GDN+QSA Hybrid architecture: Following the architectural design introduced in Qwen3.5, Qwen3.8-Flash-Next adopts a GDN + Attention hybrid architecture: out of every 4 layers, 3 GDN layers compress history into a fixed-size state, while the remaining layer performs precise retrieval over the full context. For the global Attention layers, Qwen3.8-Flash-Next further introduces Qwen Sparse Attention (QSA) to address the fact that both computation and KV cache memory-access cost grow substantially as the context lengthens. Sparse attention reduces long-sequence computation by attending only to important context. QSA goes one step further: it aggregates the sequence into micro-blocks, estimates importance at the block level, and then selects the most relevant regions, reducing both the indexing overhead and the attention cost at the same time.
- Gated Residual (GR): combines two ideas: following Hyper-Connection, it widens the residual stream into multiple branches; and it brings GatedNorm-style element-wise dynamic gating into the residual read. The original single residual stream is expanded into 4 parallel branches, allowing the model to decide dynamically, based on the current content, how much information to read from each branch and how much to write back.
- N-gram Embedding: Lookups are performed using the local context formed by "the current token plus several preceding tokens", providing additional representations for common phrases and local patterns while adding almost no per-token compute overhead. The N-gram Embedding can reside entirely in host memory to save GPU memory: lookup positions are computed in advance and asynchronously prefetched, so it never permanently occupies GPU memory. In the end, the model uses only a single N-gram Embedding layer near the start of the network, adding a large-scale "local-pattern memory" at relatively low cost.
- IndexShare MTP: the QSA top-k selection computed by the draft-extend pass over the tokens the target just accepted is held for the whole MTP iteration, so every draft decode step skips the indexer and reads that frozen selection plus the positions drafted since. At long context lengths, this substantially speeds up the MTP draft steps.
Qwen Sparse Attention: Retrieve Coarsely, Attend Precisely
Qwen3.8-Flash-Next uses compressed QSA with a compression ratio of 4, or c4. Each QSA layer has two paths: a lightweight indexer decides where to look, while sparse GQA reads the selected entries from the original attention K/V cache.
The indexer projects four 128-dimensional query heads and one shared key head. Every four raw index keys are averaged in FP32, normalized, and rotated with the first token's MRoPE position to form one compressed key. A query scores the visible compressed blocks with
QSA keeps the best 512 blocks, expands them back to 2048 logical token positions, and appends the zero-to-three tokens in the current incomplete block. The final sparse attention therefore sees at most 2051 positions. Importantly, the compressed keys are only an index: the final softmax and value aggregation use the original, uncompressed K/V.
This means QSA trades a small amount of cache capacity for much lower long-context compute and memory traffic. The indexer scans roughly small keys, then sparse attention reads about 2K full K/V entries instead of all . The model-level KV saving comes from the hybrid layout: only 12 of 48 layers store growing attention K/V, while the other 36 GDN layers use fixed-size state, not from discarding K/V inside a QSA layer.
SGLang attaches the indexer only to the full-attention layers and reuses their MRoPE implementation. The original K/V stays in the normal paged pool. QSA adds one BF16 compressed index key per four tokens; the raw keys for the unfinished block live in a four-slot per-request ring. This avoids retaining raw index keys for the full context and reduces QSA's index-cache overhead by 80%. Page-aligned full_slot / 4 addressing lets the compressed cache follow Radix Cache ownership without a separate lifecycle.
For prefill, a custom GPU kernel computes the index scores, a fast top-k selects the blocks, and Triton expands the indices and runs sparse GQA. Decode uses a paged version of the same scorer, compacts the selected original K/V, and dispatches to TRTLLM-Gen on Blackwell or packed FlashAttention otherwise. The indexer can overlap the main Q/K/V projection on a second CUDA stream, and the metadata paths are CUDA-graph compatible.
IndexShare MTP: Reusing the QSA Selection Across Draft Steps
A QSA layer runs an indexer that picks which tokens to attend, then a sparse attention over exactly those tokens. The second stage has a fixed token budget; the first scores its query against all ⌈L/4⌉ compressed blocks, so beyond a few thousand tokens the indexer, not the attention it feeds, is what sets the cost of the layer. Speculative decoding multiplies it: with --speculative-num-steps N, one MTP iteration spends N indexer invocations (N - 1 draft decode forwards plus one draft-extend) to advance the draft by at most N positions.
So the draft decode steps stop running the indexer altogether. Every MTP iteration opens with a draft-extend over the tokens the target just accepted, and that pass runs the indexer anyway; each request's last accepted row is captured there and reused by the whole draft loop, with N + 1 extra columns filled at lookup with the positions drafted since the capture, so the draft still sees its own in-flight tokens. The selection is a list of logical token indices and a request only ever grows, so it can never go out of range; and because the query has moved by at most N positions out of L, the reused ranking is essentially the one the indexer would have recomputed; accept length is unchanged. The draft's indexer work per MTP iteration drops from N invocations to one. The small metadata kernels that exist only to feed it, including the compressed decode view and the pending-ring and group-ring layouts, are removed from the draft decode step as well.
HyperConnection Kernel Optimizations
HyperConnection (HC) maintains four parallel residual streams, while Attention and MoE operate on a single hidden state. Each block therefore uses Mix to read from the four streams and Combine to write its output back. Here, M is the number of tokens processed by one call: it is small during decode and speculative verification, but can reach thousands during prefill. We dispatch to different kernels according to M.
Mix
Mix uses a low-rank projection to generate element-wise gates and reduce the four residual streams into one hidden state. For M ≤ 16, we use the low-latency split-K CuTe GEMM from FlashInfer PR #4266. Split-K partitions the K dimension so multiple CTAs can process the same output region in parallel, compensating for the limited M-dimension parallelism. SiLU, Sigmoid, gating, and the final reduction are fused into the two GEMM epilogues, avoiding intermediate writes to global memory. The up-projection weights are reordered offline so the four gate values for each output can be reduced locally inside a tile. For larger M, the implementation uses cuBLAS, which is more efficient at these shapes.
On NVIDIA B300 at M = 4, the fused path reduces Mix latency from 12.36 to 6.03 µs, a 2.05× kernel-level speedup. In an end-to-end speculative-decode benchmark against the previous Triton path, throughput improves by 7.6%.
Combine
Combine computes four injection coefficients and applies a residual update to the four streams. For large M, one fused kernel processes each token row in a single pass. At small M, this mapping exposes too few CTAs, so the M ≤ 32 path splits each row along the hidden dimension. The resulting two-kernel implementation provides enough parallelism while preserving the reference FP32 accumulation order and bitwise-identical outputs.
At M = 4, the split path reduces Combine latency from 4.17 to 2.13 µs, a 1.96× kernel-level speedup. In a separate end-to-end benchmark against the original one-CTA-per-row kernel, throughput improves by 5.49%. For large M, the fused kernel is up to 2.54× faster than the cuBLAS-based baseline and reaches 6144 GB/s of effective bandwidth.
Shape-aware dispatch lets HC use the appropriate execution path for both low-latency decode and large-scale prefill.
Per-Layer Embeddings (PLE)
Architecture
This model places PLE, a hash-addressed learned N-gram embedding memory, at the second decoder block (configured layer ID 2, corresponding to zero-based index 1). Its 51.2 billion embedding parameters, about 95.4 GiB in BF16, are fixed model weights rather than KV cache or mutable attention memory.
For token x_t, eight 2-gram hash heads use (x_{t-1}, x_t) and eight 3-gram hash heads use (x_{t-2}, x_{t-1}, x_t), producing 16 embedding row IDs. Each row contributes 160 values, which are concatenated into E_t with shape [2560].
PLE at the second decoder block. Sparse N-gram retrieval is gated into four HC branches before HC Mix. SGLang moves the vocabulary-parallel table shard to pinned host memory and gathers only the 16 selected rows per token.
The fourth line forms the PLE delta by adding the gated value to its short-conv output; the fifth injects that delta into the HC state. PLE keeps two request-local states: the two recent token IDs used for hashing and a short-conv history of shape [10240, 9]. The target model retains PLE during prefill, decode, and target verification; only the one-layer MTP draft model disables it.
Sparse Pinned-Host Offload
Because each token touches only 16 rows, SGLang keeps each rank's vocabulary-parallel table shard in pinned host memory and gathers the selected rows into a small BF16 GPU buffer with a Triton UVA kernel. A dedicated CUDA stream overlaps the gather with the first decoder block. The existing TP reduction and DP gather/scatter paths are preserved: offload changes storage location, not table ownership or PLE math. This CUDA path is enabled by default when the effective model dtype is BF16 and remains separate from KV-cache or generic layer offload.
On H200 with TP4 and MTP-213 (2 draft steps, top-k 1, and 3 draft tokens per target verification), offload reduced target-model weights from 83.91 to 60.45 GiB per GPU (-23.46 GiB) and increased allocated KV capacity from 1.84M to 3.28M tokens (+78.54%) at the same memory fraction. With 1, 2, and 4 concurrent requests, matched throughput was effectively unchanged (-0.07% geometric mean). Four fixed prompts with 128 generated tokens each matched exactly in output IDs; the recorded chosen-token logprob trace for the first case also matched exactly.
Acknowledgments
This work was a collaboration among the SGLang team at RadixArk, Qwen, NVIDIA, and AMD.
SGLang Community: Qiaolin Yu, Yuhao Yang, Cheng Wan, Xinyuan Tong, Zijie Xia, Ke Bao, Mingyi Lu, Haoguang Cai, Banghua Zhu, Ying Sheng
Qwen: Yi Zhang, Yizhong Cao, Guangda Liu
AMD: Andy Luo, Haichen Zhang
NVIDIA: NVIDIA and SGLang jointly optimized Qwen3.8-Flash-Next performance on Blackwell and Hopper.