🇨🇳 Huawei just released breakthrough chip design approach "LogicFolding" that will close it's gap with TSMC.

The technical paper behind it.

The core idea is that chips should stop measuring progress mainly by how small transistors are and start measuring progress by how much time delay can be removed from the whole machine.

A chip wastes time when signals move through long wires， memory paths， chip-to-chip links， and software communication layers， so Huawei calls this delay τ， or tau.

Huawei's paper introducing "LogicFolding" says the next chip breakthrough may come from cutting wasted time inside the machine.

That is what "τ scaling" means.

τ is the delay that accumulates before useful computing happens： a transistor switches， a signal crosses a wire， data reaches memory， a chip talks to another chip， or a server waits for a response.

Moore's Law reduced this delay indirectly because shrinking transistors also shortened many of the paths around them.

But modern chips are no longer slowed only by transistor size.

They are slowed by wire resistance， parasitic capacitance， clock skew， memory distance， protocol conversion， chip-to-chip communication， and the cost of moving data.

So τ scaling changes the question from "how small is the transistor？" to "where is time being lost？"

LogicFolding is Huawei's physical answer to that question inside a chip.

In a normal chip， related logic gates are spread across a flat surface， so signals often travel sideways through long metal routes before reaching the next important gate.

Those wires behave like sticky pipes： resistance slows current， capacitance must be charged and discharged， and every extra distance creates delay and wastes energy.

LogicFolding tries to stack active circuit layers vertically and connect them with very fine hybrid bonds， so circuits that need to talk are placed above and below each other instead of far apart on one plane.