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Rohan Paul@rohanpaul_ai
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2026-05-25 19:07· 72天前
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华为提出了“τ缩放”和“LogicFolding”两种新方法，旨在不依赖最先进光刻工具的前提下，缩小与台积电的性能差距。其核心思想是将衡量芯片进步的指标从晶体管尺寸转向信号传输延迟（τ）。LogicFolding作为具体实现，通过垂直堆叠逻辑电路层并采用混合键合，将需要通信的电路紧邻放置，从而缩短关键线路、降低电阻和寄生电电容，提升信号速度。华为表示，其下一代麒麟手机芯片将是对τ缩放规律的首次全面测试。

🇨🇳 Huawei just released breakthrough chip design approach "LogicFolding" that will close it's gap with TSMC.

The technical paper behind it.

The core idea is that chips should stop measuring progress mainly by how small transistors are and start measuring progress by how much time delay can be removed from the whole machine.

A chip wastes time when signals move through long wires， memory paths， chip-to-chip links， and software communication layers， so Huawei calls this delay τ， or tau.

Huawei's paper introducing "LogicFolding" says the next chip breakthrough may come from cutting wasted time inside the machine.

That is what "τ scaling" means.

τ is the delay that accumulates before useful computing happens： a transistor switches， a signal crosses a wire， data reaches memory， a chip talks to another chip， or a server waits for a response.

Moore's Law reduced this delay indirectly because shrinking transistors also shortened many of the paths around them.

But modern chips are no longer slowed only by transistor size.

They are slowed by wire resistance， parasitic capacitance， clock skew， memory distance， protocol conversion， chip-to-chip communication， and the cost of moving data.

So τ scaling changes the question from "how small is the transistor？" to "where is time being lost？"

LogicFolding is Huawei's physical answer to that question inside a chip.

In a normal chip， related logic gates are spread across a flat surface， so signals often travel sideways through long metal routes before reaching the next important gate.

Those wires behave like sticky pipes： resistance slows current， capacitance must be charged and discharged， and every extra distance creates delay and wastes energy.

LogicFolding tries to stack active circuit layers vertically and connect them with very fine hybrid bonds， so circuits that need to talk are placed above and below each other instead of far apart on one plane.

The signal now takes a shorter route， the critical path becomes faster， clock timing becomes cleaner， and the same manufacturing node can deliver more performance.

Huawei is trying to win not by making every switch smaller， but by making every important signal travel less， wait less， and arrive sooner.

Rohan Paul🇨🇳 Huawei reveals a new chip design breakthrough under US sanctions pressure. A design approach meant to close the gap with TSMC and Intel without relying onl...
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来源：Rohan Paul · x.com

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Rohan Paul · @rohanpaul_ai · X·2026-05-25 19:07·72天前
AI 导读

华为提出了“τ缩放”和“LogicFolding”两种新方法，旨在不依赖最先进光刻工具的前提下，缩小与台积电的性能差距。其核心思想是将衡量芯片进步的指标从晶体管尺寸转向信号传输延迟（τ）。LogicFolding作为具体实现，通过垂直堆叠逻辑电路层并采用混合键合，将需要通信的电路紧邻放置，从而缩短关键线路、降低电阻和寄生电电容，提升信号速度。华为表示，其下一代麒麟手机芯片将是对τ缩放规律的首次全面测试。

🇨🇳 Huawei just released breakthrough chip design approach "LogicFolding" that will close it's gap with TSMC.

The technical paper behind it.

The core idea is that chips should stop measuring progress mainly by how small transistors are and start measuring progress by how much time delay can be removed from the whole machine.

A chip wastes time when signals move through long wires， memory paths， chip-to-chip links， and software communication layers， so Huawei calls this delay τ， or tau.

Huawei's paper introducing "LogicFolding" says the next chip breakthrough may come from cutting wasted time inside the machine.

That is what "τ scaling" means.

τ is the delay that accumulates before useful computing happens： a transistor switches， a signal crosses a wire， data reaches memory， a chip talks to another chip， or a server waits for a response.

Moore's Law reduced this delay indirectly because shrinking transistors also shortened many of the paths around them.

But modern chips are no longer slowed only by transistor size.

They are slowed by wire resistance， parasitic capacitance， clock skew， memory distance， protocol conversion， chip-to-chip communication， and the cost of moving data.

So τ scaling changes the question from "how small is the transistor？" to "where is time being lost？"

LogicFolding is Huawei's physical answer to that question inside a chip.

In a normal chip， related logic gates are spread across a flat surface， so signals often travel sideways through long metal routes before reaching the next important gate.

Those wires behave like sticky pipes： resistance slows current， capacitance must be charged and discharged， and every extra distance creates delay and wastes energy.

LogicFolding tries to stack active circuit layers vertically and connect them with very fine hybrid bonds， so circuits that need to talk are placed above and below each other instead of far apart on one plane.

The signal now takes a shorter route， the critical path becomes faster， clock timing becomes cleaner， and the same manufacturing node can deliver more performance.

Huawei is trying to win not by making every switch smaller， but by making every important signal travel less， wait less， and arrive sooner.

Rohan Paul🇨🇳 Huawei reveals a new chip design breakthrough under US sanctions pressure. A design approach meant to close the gap with TSMC and Intel without relying onl...

来源：Rohan Paul· x.com

端侧论文/研究
事件后续 · 1查看事件全部 →